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STM8S003F3P6 STM32F103C8T6

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STM8S003F3P6 STM32F103C8T6

名称深圳市斯瑞特科技有限公司【公司网站】
所在地中国广东深圳
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价格 ￥3.6元/件 点此议价
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发布日期 2020-06-12 14:12 至长期有效

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STM8S003F3P6 STM32F103C8T6产品详情

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STM32F103C8T6:STM32F103C8T6
品牌:ST/意法半导体
封装形式:DIP
类型:其他
型号:STM32F103C8T6
批号:2017+

LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD co*ollers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-

effective graphic applicati* using LCD modules with embedded co*ollers or high-

performance soluti* using external co*ollers with dedicated acceleration.

2.3.7

Nested vectored interrupt co*oller (NVIC)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested

vectored interrupt co*oller able to handle up to 60 maskable interrupt channels (not

including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

●

Closely coupled NVIC gives low latency interrupt processing

●

Interrupt e*y vector table addres*ssed directly to the core

●

Closely coupled NVIC core interface

●

Allows early processing of interrupts

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Processing of late arriving higher priority interrupts

●

Support for tail-chaining

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Processor state automatically s*ed

●

Interrupt e*y restored on interrupt exit with no instruction overhead

This ha*are block provides flexible interrupt management features with minimal interrupt

latency.

2.3.8

External interrupt/event co*oller (EXTI)

The external interrupt/event co*oller c*ists of 19 edge detector lines used to generate

interrupt/eve*equests. Each line can be independently configured to select the tri*er

eve*ising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected

to the 16 external interrupt lines.

2.3.9

Clocks and startup

System clock selection is performed*tartup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it i*onitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt manageme*f the PLL clock e*y is *ailable when necessary (for example with

failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the high speed APB

(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and

the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed

APB domain is 36 MHz. See Figure 2 for details on the clock tree

以上内容为STM8S003F3P6 STM32F103C8T6，本产品由深圳市斯瑞特科技有限公司直销供应。

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