STM8S105C6T6 STM32F407ZET6

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STM8S105C6T6 STM32F407ZET6

名称深圳市斯瑞特科技有限公司【公司网站】
所在地中国广东深圳
联系人 朱小姐
价格 ￥3.03元/件 点此议价
采购量不限制
发布日期 2020-06-12 14:11 至长期有效

热线：13560767759

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STM8S105C6T6 STM32F407ZET6产品详情

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STM32F407ZET6:STM32F407ZET6
品牌:ST/意法半导体
封装形式:DIP
类型:数字集成电路
用途:军工
功能:单片机
导电类型:双极型
封装外形:金属壳圆形型
集成度:小规模(<50)
型号:STM32F407ZET6
批号:2017+

<*n class="ft6">Single DMA and burst DMA request signals. Each peripheral connected to the

GPDMA can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the GPDMA.

• <*n class="ft6">Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers.

• <*n class="ft6">Scatter or gather DMA is supported through the use of linked lists. Thi*eans that

the source and destination areas do not h*e to occupy contiguous areas of memory.

• <*n class="ft6">Ha*are DMA channel priority. Each DMA channel has a specific ha*are priority.

DMA channel 0 has the highest priority and channel 1 has the lowest priority. If

requests from two channels become active at the same time the channel with the

highest priority is serviced first.

• <*n class="ft6">AHB sl*e DMA programming interface. The GPDMA is programmed by writing to the

DMA co*ol registers over the AHB sl*e interface.

• <*n class="ft6">One AHB bu*aster for transferring data. This interface transfers data when a DMA

request goes active.

• <*n class="ft6">32-bit AHB master bus width.

• <*n class="ft6">Incrementing or non-incrementing addressing for source and destination.

• <*n class="ft6">Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the

peripheral.

• <*n class="ft6">Internal four-word FIFO per channel.

• <*n class="ft6">Supports 8-bit, 16-bit, and 32-bit wide transacti*.

• <*n class="ft6">An interrupt to the processor can be generated on a DMA completion or when a DMA

error has occurred.

• <*n class="ft6">Interrupt masking. The DMA error and DMA terminal count interrupt requests can be

masked.

• <*n class="ft6">Raw interrupt status. The DMA error and DMA cou*aw interrupt status can be read

prior to masking.

以上内容为STM8S105C6T6 STM32F407ZET6，本产品由深圳市斯瑞特科技有限公司直销供应。

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